The present application relates generally to semiconductor devices, and particularly to vertical fin field effect transistors (V-FinFETs) and their methods of fabrication.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around or formed over the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 20 nm wide or less, on the surface of a substrate using selective-etching techniques. A gate structure is then deposited to contact multiple surfaces of each fin to form a multi-gate architecture.
Vertical FETs are devices where the source-drain current flows in a direction normal to the substrate surface. In vertical FinFET devices, the fin defines the transistor channel with the source and drain regions located at opposing (i.e., upper and lower) ends of the fin.
During manufacture of a vertical FET, the channel length is typically defined by etch back of the gate conductor. A challenge associated with a vertical FET architecture is the ability to co-integrate devices having different channel lengths on the same substrate or chip. Moreover, the formation of long channel devices, such as where the channel length exceeds the height of the fin, is problematic. Accordingly, it would be advantageous to provide a robust, vertical FinFET manufacturing process and associated structure that are compatible with existing circuit designs, while providing a variable channel length, i.e., both short and long channel devices, on a common platform.